The complete guide · PCB fabrication
How to specify a PCB for fabrication, step by step
Everything a board house needs to build exactly what your layout intends — stackup, copper, geometry, impedance, finish, class, and files — with the rules of thumb and the flags that separate a working board from a requote.
The short version
- Layer count is an EMC decision — high-speed signals on 2 layers is the classic false economy — 4 layers buys return planes.
- Copper weight follows current — 1 oz default; wide pours or heavier copper once any trace carries amps.
- 6/6 mil is the standard floor — sub-4-mil trace/space moves you into premium fab pricing for nothing if you don't need it.
- Impedance needs a stackup reference — “50 Ω ±10%” is meaningless without naming the layers and dielectric it's built on.
- Finish by assembly need — ENIG for fine-pitch/BGA and RF; HASL is fine for coarse commodity boards.
- Name the class and the tests — IPC-6012 Class 2 + 100% electrical test is the sane default.
01Choose the layer count for signal integrity, not just cost
Two layers look cheaper until the EMC scan. Anything with fast edges — crystals above a few MHz, USB, Ethernet, RF — wants an unbroken return plane under it, which is what layer 2 of a 4-layer board is for.
Rule: high-speed or RF content → 4+ layers with a solid ground plane adjacent to the signal layer. A 2-layer board carrying USB is the classic physics flag: the redesign after the failed EMC test costs more than the two layers ever saved.
02Set copper weight from the current budget
Trace heating follows current density. Standard 1 oz copper handles signal-level current forever; power paths need width, weight, or both — worked out, not hoped.
Per IPC-2152 rules of thumb at 1 oz external: ~0.6 mm width per amp for a 10 °C rise. Above ~3–5 A, use pours or step to 2 oz; above ~10 A think busbar or dedicated power planes. State copper weight per layer: “1 oz outer / 0.5 oz inner”.
03Hold the 6/6 mil floor unless density forces you down
Minimum trace/space sets which fab lines can build your board and at what yield. Every fab quotes 6/6 mil routinely; below 4/4 you enter advanced-process pricing.
State your actual minimums: “min trace/space 6/6 mil; min drill 0.3 mm”. If your layout only needs fine geometry under one BGA, say so — some fabs price by the tightest feature anywhere, and needless 3-mil callouts buy premium pricing for nothing.
04Specify controlled impedance against a named stackup
“50 Ω” floats free until it references physical layers: which signal layer, over which plane, in what dielectric. The fab tunes trace width to hit impedance IN a stackup — so the spec must marry them.
Pattern: “50 Ω ±10% single-ended, L1 over L2 plane; 90 Ω ±10% differential (USB), per attached stackup drawing”. Ask the fab to confirm final widths against their materials — deferred by name, not omitted.
05Pick the surface finish for how the board is assembled
The finish is the surface your solder joints form on. HASL (solder-leveled) is cheap and fine for coarse-pitch work; its uneven surface is wrong under BGAs and its thickness variation is wrong for RF structures.
Rule: fine-pitch (≤0.5 mm), BGA, or RF → ENIG; commodity through-hole and coarse SMD → HASL (lead-free). Say which — and note any gold fingers or press-fit areas that need their own finish callout.
06Name the fabrication class and the testing
IPC-6012 classes set workmanship and inspection: Class 2 for commercial products, Class 3 where failure is not an option (and where cost rises to match). Untested boards are a lottery ticket.
Default: “IPC-6012 Class 2; 100% electrical test (netlist)”. Specify Class 3 only where the product truly warrants it — it changes annular ring, plating, and inspection requirements throughout.
07Ship the complete file package, and defer the rest
A fab builds exactly what the files say. The stall-your-quote classics: gerbers without a drill file, impedance callouts without a stackup drawing, no netlist to e-test against.
The package: gerbers + NC drill + stackup drawing + IPC-356 netlist + a fab-notes drawing carrying everything above (material “FR-4, Tg150”, thickness “1.6 mm ±10%”, soldermask/silk colors, quantity + panelization preference). Defer by name: panel design, exact impedance widths, via plating process.
Worked example: an IoT sensor board
The whole chain, numbers shown — the same derivations the SpecBuildr interview performs and prints in your spec's math appendix.
Layers / material4-layer, FR-4 Tg150, 1.6 mm ±10%
StackupL1 sig / L2 GND / L3 PWR / L4 sig, per drawing
Copper1 oz outer, 0.5 oz inner; 5 V pour sized for 3 A
Geometry6/6 mil trace/space; 0.3 mm min drill; via-in-pad none
Impedance50 Ω ±10% SE (antenna feed, L1/L2); 90 Ω ±10% diff (USB)
FinishENIG (0.4 mm-pitch BGA + RF feed); green mask, white silk
Class / testIPC-6012 Class 2; 100% e-test to IPC-356 netlist
Quantity50 boards; fab may panelize; gerbers+drill+stackup+netlist attached
The mistakes that make quotes expensive
✗USB/RF on a 2-layer board
No return plane, no EMC pass. The 4-layer upcharge is cheaper than the respin.
✗Sub-4-mil geometry without needing it
One needless 3-mil callout prices the whole board on an advanced line.
✗“50 Ω” with no stackup reference
Impedance is a geometry+dielectric outcome. Without the stackup drawing the number is decoration.
✗HASL under a BGA or RF structure
The uneven, variable-thickness surface causes opens under fine-pitch parts and detunes RF. ENIG.
✗No netlist in the package
Without IPC-356 the fab cannot e-test; you get visually-inspected boards and field failures.
Frequently asked questions
What does a PCB fab actually need to quote and build my board?
Gerbers, NC drill, a stackup drawing, an IPC-356 netlist, and a fab notes drawing stating: layers, material and thickness, copper weights, minimum trace/space and drill, impedance targets referenced to the stackup, surface finish, soldermask/silkscreen, IPC-6012 class, testing, and quantity.
How many layers does my PCB need?
Two layers suit low-speed, low-density boards. Once you carry fast edges — USB, Ethernet, RF, fast clocks — you want 4+ layers so every high-speed trace runs over an unbroken ground plane. The EMC failure costs more than the extra layers.
Should I choose ENIG or HASL surface finish?
ENIG for fine-pitch (≤0.5 mm), BGAs, and RF — it is flat and uniform. Lead-free HASL is fine (and cheaper) for coarse-pitch commodity boards. The wrong choice shows up as assembly defects, not fab defects.
What is IPC-6012 Class 2 vs Class 3?
Workmanship classes: Class 2 is the commercial-product default; Class 3 (high-reliability) tightens plating, annular ring, and inspection for aerospace/medical/safety applications — at a real cost premium. Specify 3 only when the product demands it.
Can I write a PCB fab spec without being a hardware engineer?
Yes — the SpecBuildr interview asks about your signals, power, and parts in plain language, then generates the fab spec with the physics flags applied: layer count vs. signal speed, copper vs. current, finish vs. component pitch.
Skip the blank page
The interview asks you these exact questions in plain language, runs the physics checks, and prints a complete, quotable spec — free.
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